The present invention relates to a data transfer controller in a data processing system and, more particularly, to a data transfer controller for transferring vector data from a main memory to a vector data processor.
Strong demand has arisen for high-speed supply of a large amount of data to allow high-speed vector calculations in a high-speed vector computer used in scientific calculations. In order to allow high-speed supply of a large amount data, for example, U.S. Pat. No. 4,128,880 discloses a vector processor. In this vector processor, the number of independently operable banks is increased to read out elements of vector data every clock cycle, and the readout elements are supplied to vector registers. When the first element is supplied to the vector register, a vector calculation is started.
In this conventional vector processor, since only one element of the vector data is supplied to the vector register every clock cycle, when a calculation is performed between two vector data, the vector calculation cannot be started until transfer of the second vector data is started. In order to solve this problem, there is a conventional method of simultaneously reading out elements of two vector data from a memory. In this case, bank busy management of the two different vector data must be performed to complicate the control.